Computer Vision Algorithms on Reconfigurable Logic Arrays

Computer Vision Algorithms on Reconfigurable Logic Arrays By Nalini K. Ratha Computer vision algorithms are natural candidates for high performance computing due to their inherent parallelism and intense computational demands. For example, a simple 3 3 convolution on a 512 512 gray scale image at 30 frames per second requires 67.5 million multiplications and 60 million additions to be performed in one second. Computer vision tasks can be classi ed into three categories based on their computational complexity and communication complexity: low-level, intermediate-level and high-level. Special-purpose hardware provides better performance compared to a general-purpose hardware for all the three levels of vision tasks. With recent advances in very large scale integration (VLSI) technology, an application speci c integrated circuit (ASIC) can provide the best performance in terms of total execution time. However, long design cycle time, high development cost and in exibility of a dedicated hardware deter design of ASICs. In contrast, eld programmable gate arrays (FPGAs) support lower design veri cation time and easier design adaptability at a lower cost. Hence, FPGAs with an array of recon gurable logic blocks can be very useful compute elements. FPGA-based custom computing machines are playing a major role in realizing high performance application accelerators. Three computer vision algorithms have been investigated for mapping onto custom computing machines: (i) template matching (convolution) { a low level vision operation (ii) texture-based segmentation { an intermediate-level operation, and (iii) point pattern matching { a high level vision algorithm. The advantages demonstrated through these implementations are as follows. First, custom computing machines are suitable for all the three levels of computer vision algorithms. Second, custom computing machines can map all stages of a vision system easily. This is unlike typical hardware platforms where a separate subsystem is dedicated to a speci c step of the vision algorithm. Third, custom computing approach can run a vision application at a high speed, often very close to the speed of special-purpose hardware. The performance of these algorithms on Splash 2 { a Xilinx 4010 eld programmable gate array-based custom computing machine { is near ASIC level of speed. A taxonomy involving custom computing platforms, special purpose vision systems, general purpose processors and special purpose ASICs has been constructed using several comparative features characterizing these systems and standard hierarchical clustering algorithms. The taxonomy provides an easy way of understanding the features of custom computing machines. To my parents | Thank you for your constant encouragement for higher academic pursuits. iv Acknowledgments I take this oppurtunity to express my deep sense of gratitude to my advisor Dr. Anil K. Jain for having having recruited me into the Ph. D. program and assigning me this wonderful thesis topic. His support, encouragement and above all constant monitoring and guidance kept me involved in the project leading to successful completion of my degree. I consider myself very lucky for having worked with such a great personality and mentor. I wish to thank my committee members Dr. Lionel M. Ni, Dr. John Weng, Dr. Diane T. Rover and Dr. V. Mandrekar for serving on my committee and contributing towards enhancing the quality of my thesis in several ways. This research work was supported by nancial assistance from the Department of Defense. I acknowledge their support. In particular, help from Dr. D. A. Buell, Dr. Je Arnold and Mr. Brian Schott of Center for Computing Research, Bowie, Maryland, is greatly appreciated. Several long hours of discussion with Brian and his personal help in making me understand programming on Splash 2 has helped me in a big way. In addition, I wish to thank Dr. Sea H. Choi for his assistance in VHDL related problems. As a project investigator, Dr. Rover was very helpful, easily v accessible and took care of many issues to make the project very successful. I thank her for her assistance. The Pattern Recognition and Image Processing (PRIP) laboratory provided one of the nest and up-to-date computing facilities for this reseach. I thank the PRIP Lab managers Lisa Lees, Hans Dulimarta and Karissa Miller for their dedicated e orts in making the PRIP lab a great place to work. I have personally bene ted from all the PRIPpies, both past and present, for their help and support over my stay at MSU. I thank them all. Special thanks are due to Aditya and Prasoon for their help in proof reading my draft version of the thesis. Last but not the least, I thank my wife Meena for her unfailing support, understanding and help in successful completion of this thesis. Her encouragement kept me motivated even during the most di cult periods. vi Table of